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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9884a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 100 msps/140 msps analog flat panel interface general description the ad9884a is a complete 8-bit 140 msps monolithic analog interface optimized for capturing rgb graphics signals from personal computers and workstations. its 140 msps encode rate capability and full-power analog bandwidth of 500 mhz supports display resolutions of up to 1280 1024 (sxga) at 75 hz with sufficient input bandwidth to accurately acquire and digitize each pixel. to minimize system cost and power dissipation, the ad9884a includes an internal +1.25 v reference, pll to generate a pixel clock from hsync, and programmable gain, offset and clamp circuits. the user provides only a +3.3 v power supply, analog input, and hsync signals. three-state cmos outputs may be powered by a supply between 2.5 v and 3.3 v. the ad9884as on-chip pll generates a pixel clock from the hsync input. pixel clock output frequencies range from features 140 msps maximum conversion rate 500 mhz analog bandwidth 0.5 v to 1.0 v analog input range 400 ps p-p pll clock jitter power-down mode 3.3 v power supply 2.5 v to 3.3 v three-state cmos outputs demultiplexed output ports data clock output provided low power: 570 mw typical internal pll generates clock from hsync serial port interface fully programmable supports alternate pixel sampling for higher- resolution applications applications rgb graphics processing lcd monitors and projectors plasma display panels scan converters functional block diagram sda scl a 0 a 1 pwrdn hsync coast clamp filt ckext refin ckinv refout 8 a/d clamp r in g in b in 8 a/d clamp 8 8 a/d clamp 8 ref 8 8 8 8 8 8 sogin 0.15v 2 ad9884a clock generator sogout datack r outa r outb g outa g outb b outa b outb hsout control 20 mhz to 140 mhz. pll clock jitter is typically 400 ps p-p relative to the input reference. when the coast signal is pre- sented, the pll maintains its output frequency in the absence of hsync. a 32-step sampling phase adjustment is provided. data, hsync and d ata clock output phase relationships are always maintained. the pll can be disabled and an external clock input provided as the pixel clock. a clamp signal is generated internally or may be provided by the user through the clamp input pin. this device is fully program- mable via a two-wire serial port. fabricated in an advanced cmos process, the ad9884a is provided in a space-saving 128-lead mqfp surface mount plas- tic package and is specified over a 0 c to +70 c temperature range.
rev. b C2C ad9884aCspecifications (v d = +3.3 v, v dd = +3.3 v, pv d = +3.3 v, adc clock frequency = maximum, pll clock frequency = maximum, control registers programmed to default state) test ad9884aks-100 ad9884aks-140 parameter temp level min typ max min typ max unit resolution 8 8 bits dc accuracy differential nonlinearity +25 ci 0.5 1.0 0.5 +1.15/C1.0 lsb full vi 1.0 +1.25/C1.0 lsb integral nonlinearity +25 ci 0.5 1.25 0.8 1.4 lsb full vi 1.75 2.5 lsb no missing codes full vi guaranteed guaranteed analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco +25 c v 100 280 ppm/ c input bias current +25 ci 1 1 m a full vi 1 1 m a input offset voltage full vi 7 50 7 50 mv input full-scale matching full vi 1.5 5.0 1.5 5.0 %fs offset adjustment range full vi 22 23.5 25 22 23.5 25 %fs reference output output voltage full vi +1.20 +1.25 +1.30 +1.20 +1.25 +1.30 v temperature coefficient full v 50 50 ppm/ c switching performance maximum conversion rate full vi 100 140 msps minimum conversion rate full iv 10 10 msps data to clock skew, t skew full iv C0.5 +2.0 C0.5 +2.0 ns t buff full vi 4.7 4.7 m s t stah full vi 4.0 4.0 m s t dho full vi 0 0 m s t dal full vi 4.7 4.7 m s t dah full vi 4.0 4.0 m s t dsu full vi 250 250 ns t stasu full vi 4.7 4.7 m s t stosu full vi 4.0 4.0 m s hsync input frequency full iv 15 110 15 110 khz maximum pll clock rate full vi 100 140 mhz minimum pll clock rate full iv 20 20 mhz pll jitter +25 c iv 400 700 1 475 750 2 ps p-p full iv 1000 1 1000 2 ps p-p sampling phase tempco full iv 15 15 ps/ c digital inputs input voltage, high (v ih ) full vi 2.5 2.5 v input voltage, low (v il ) full vi 0.8 0.8 v input current, high (i ih ) full vi C1.0 C1.0 m a input current, low (i il ) full vi 1.0 1.0 m a input capacitance +25 cv 3 3 pf digital outputs output voltage, high (v oh ) full vi v dd C 0.1 v dd C 0.1 v output voltage, low (v ol ) full vi 0.1 0.1 v duty cycle datack, datack full iv 45 50 55 45 50 55 % output coding binary binary
rev. b C3C ad9884a test ad9884aks-100 ad9884aks-140 parameter temp level min typ max min typ max unit power supply v d supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v v dd supply voltage full iv 2.2 3.3 3.6 2.2 3.3 3.6 v pv d supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v i d supply current (v d ) +25 c v 125 135 ma i dd supply current (v dd ) 3 +25 c v 33 47 ma ipv d supply current (pv d ) +25 c v 15 15 ma total power dissipation full vi 570 675 650 775 mw power-down supply current full vi 2.0 25 2.0 25 ma power-down dissipation full vi 6.6 82.5 6.6 82.5 mw dynamic performance analog bandwidth, full power +25 c v 500 500 mhz transient response +25 cv 2 2 ns overvoltage recovery time +25 c v 1.5 1.5 ns signal-to-noise ratio (snr) 4 +25 c i 44.0 46.5 43.5 46.2 db (without harmonics) full v 46.0 45.0 db f in = 40.7 mhz crosstalk full v 60 60 dbc thermal characteristics q jc Cjunction-to-case thermal resistance v 8.4 8.4 c/w q ja Cjunction-to-ambient thermal resistance v 35 35 c/w notes 1 vcornge = 01, current = 001, plldiv = 1693 10 . 2 vcornge = 10, current = 110, plldiv = 1600 10 . 3 demux = 1; datack and datack load = 15 pf; data load = 5 pf. 4 using external pixel clock. specifications subject to change without notice. ordering guide temperature package package model range description option ad9884aks-140 0 c to +70 c mqfp s-128 ad9884aks-100 0 c to +70 c mqfp s-128 ad9884a/pcb +25 c evaluation board explanation of test levels test level i. 100% production tested. ii. 100% production tested at +25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at +25 c; guaranteed by design and characterization testing. absolute maximum ratings * v d, pv d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to +4 v pv d to v d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to +4 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to C0.5 v refin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to 0.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to 0.0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . . C20 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . +175 c maximum case temperature . . . . . . . . . . . . . . . . . . +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9884a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. b ad9884a C4C table i. package interconnections signal type name function value package pin inputs r ain analog input for red channel 0.5 v to 1.0 v fs 7 g ain analog input for green channel 0.5 v to 1.0 v fs 15 b ain analog input for blue channel 0.5 v to 1.0 v fs 22 hsync horizontal sync input 3.3 v cmos 40 coast clock generator coast input (optional) 3.3 v cmos 41 clamp external clamp input (optional) 3.3 v cmos 28 sogin sync on green slicer input (optional) 0.5 v to 1.0 v fs 14 ckext external clock input (optional) 3.3 v cmos 44 ckinv sampling clock inversion (optional) 3.3 v cmos 27 outputs d r a 7-0 data output, red channel, port a 3.3 v cmos 105C112 d r b 7-0 data output, red channel, port b 3.3 v cmos 95C102 d g a 7-0 data output, green channel, port a 3.3 v cmos 85C92 d g b 7-0 data output, green channel, port b 3.3 v cmos 75C82 d b a 7-0 data output, blue channel, port a 3.3 v cmos 65C72 d b b 7-0 data output, blue channel, port b 3.3 v cmos 55C62 datack data output clock 3.3 v cmos 115 datack data output clock complement 3.3 v cmos 116 hsout horizontal sync output 3.3 v cmos 117 sogout sync on green slicer output 3.3 v cmos 118 control sda serial data i/o 3.3 v cmos 29 scl serial interface clock 3.3 v cmos 30 a 0 , a 1 serial port address lsbs 3.3 v cmos 31, 32 pwrdn power-down control input 3.3 v cmos 125 analog interface refout internal reference output +1.25 v 126 refin reference input +1.25 v 10% 127 filt external filter connection 45 power supply v d main power supply 3.3 v 10% 4, 8, 10, 11, 16, 18, 19, 23, 25, 124, 128 v dd digital output power supply 2.5 v to 3.3 v 10% 54, 64, 74, 84, 94, 104, 114, 120 pv d clock generator power supply 3.3 v 10% 33, 34, 43, 48, 50 gnd ground 0 v 5, 6, 9, 12, 13, 17, 20, 21, 24, 26, 35, 39, 42, 47, 49, 51, 52, 53, 63, 73, 83, 93, 103, 113, 119, 121, 122, 123 no connect nc 1C3, 36C38, 46
rev. b ad9884a C5C pin configuration 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 100 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 11 8 117 116 115 114 113 112 110 109 108 107 106 105 104 103 pin 1 identifier top view pins down (not to scale) v d refin refout pwrdn v d gnd gnd gnd v dd gnd sogout hsout datack datack v dd gnd d r a 0 d r a 1 d r a 2 d r a 3 hsync coast gnd pv d ckext filt nc gnd pv d gnd pv d gnd gnd gnd v dd d b b 7 d b b 6 d b b 5 d b b 4 d r b 0 d r b 1 d r b 2 d r b 3 d r b 4 d r b 5 d r b 6 d r b 7 v dd gnd d g a 0 d g a 1 d g a 2 d g b 2 d g b 3 d g b 4 d g b 5 d g b 6 d g b 7 v dd gnd nc nc nc v d gnd gnd r ain v d gnd v d v d gnd gnd sogin g ain v d gnd v d v d gnd gnd b ain v d gnd v d gnd ckinv clamp sda scl a 0 a 1 d b b 3 d b b 2 d b b 1 d b b 0 gnd v dd gnd d b a 0 d b a 1 d r a 4 d r a 5 d r a 6 d r a 7 v dd gnd d g a 3 d g a 4 d g a 5 d g a 6 d g a 7 v dd gnd d g b 0 d g b 1 ad9884a pv d pv d gnd nc nc nc d b a 2 d b a 3 d b a 4 d b a 5 d b a 6 d b a 7 nc = no connect
rev. b ad9884a C6C pin function descriptions pin name function inputs r ain analog input for red channel g ain analog input for green channel b ain analog input for blue channel high impedance inputs that accepts the red, green, and blue channel graphics signals, respectively. the three channels are identical, and can be used for any colors, but colors are assigned for convenient reference. they accommodate input signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. hsync horizontal sync input this input receives a logic signal that establishes the horizontal timing reference and provides the frequency refer- ence for pixel clock generation. the logic sense of this pin is controlled by hspol. only the leading edge of hsync is active. when hspol = 0, the falling edge of hsync is used. when hspol = 1, the rising edge is active. the input includes a schmitt trigger for noise immunity, with a nominal input threshold of 1.5 v. electrostatic discharge (esd) protection diodes will conduct heavily if this pin is driven more than 0.5 v above the 3.3 v power supply (or more than 0.5 v below ground). if a 5 v signal source is driving this pin, the signal should be clamped or current limited. coast clock generator coast input (optional) this input may be used to cause the pixel clock generator to stop synchronizing with hsync and continue pro- ducing a clock at its present frequency and phase. this is useful when processing sources that fail to produce hori- zontal sync pulses when in the vertical interval. the coast signal is generally not required for pc-generated signals. the logic sense of this pin is controlled by cstpol. coast may be asserted at any time. when not used, this pin must be grounded and cstpol programmed to 1. cstpol defaults to 1 at power-up. clamp external clamp input (optional) this logic input may be used to define the time during which the input signal is clamped to ground, establishing a black reference. it should be exercised when a black signal is known to be present on the analog input channels, typically during the back porch period of the graphics signal. the clamp pin is enabled by setting control bit extclmp to 1 (default power-up is 0). when disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the hsync input. the logic sense of this pin is controlled by clampol. when not used, this pin must be grounded and extclmp programmed to 0. sogin sync on green slicer input (optional) this input is provided to assist in processing signals with embedded sync, typically on the green channel. the pin is connected to a high speed comparator with an internally-generated threshold of 0.15 v. when connected to a dc-coupled graphics signal with embedded sync, it will produce a noninverting digital output on sogout that changes state whenever the input signal crosses 0.15 v. this is usually a composite sync signal, containing both vertical and horizontal sync information that must be separated before passing the horizontal sync signal to hsync. the sog slicer comparator continues to operate when the ad9884a is put into a power-down state. when not used, this input should be grounded. ckext external clock input (optional) this pin may be used to provide an external clock to the ad9884a, in place of the clock internally-generated from hsync. this input is enabled by programming extclk to 1. when an external clock is used, all other internal functions operate normally. when unused, this pin should be tied through a 10 k w resistor to ground, and extclk programmed to 0. the clock phase adjustment still operates when an external clock source is used. ckinv sampling clock inversion (optional) this pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180 degrees. this is in support of alternate pixel sampling mode, wherein higher frequency input signals (up to 280 mpps) may be captured by first sampling the odd pixels, then capturing the even pixels on the subsequent frame. this pin should be exercised only during blanking intervals (typically vertical blanking) as it may produce several samples of corrupted data during the phase shift. ckinv should be grounded when not used.
rev. b ad9884a C7C pin function descriptions (continued) pin name function outputs d r a 7C0 data output, red channel, port a d r b 7C0 data output, red channel, port b d g a 7C0 data output, green channel, port a d g b 7C0 data output, green channel, port b d b a 7C0 data output, blue channel, port a d b b 7C0 data output, blue channel, port b the main data outputs. bit 7 is the msb. each channel has two ports. when the part is operated in single chan- nel mode (demux = 0), all data are presented to port a, and port b is placed in a high impedance state. pro- gramming demux to 1 establishes dual channel mode, wherein alternate pixels are presented to port a and port b of each channel. these will appear simultaneously, two pixels presented at the time of every second input pixel, when par is set to 1 (parallel mode). when par = 0, pixel data appear alternately on the two ports, one new sample with each incoming pixel (interleaved mode). in dual channel mode, the first pixel sampled after hsync is routed to p ort a. the second pixel goes to port b, the third to a, etc. the delay from pixel sampling time to output is fixed. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the datack, datack and hsout outputs are also moved, so the timing relationship among the signals is maintained. datack data output clock datack data output clock complement differential data clock output signals to be used to strobe the output data and hsout into external logic. they are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. when the ad9884a is operated in single channel mode, the output frequency is equal to the pixel sampling frequ ency. when operating in dual channel mode, the data output clock and the output data are presented at one-half the pixel rate. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the data, datack, datack and hsout outputs are all moved, so the timing relationship among the signals is maintained. either or both signals may be used, depending on the timing mode and interface design employed. hsout horizontal sync output a reconstructed and phase-aligned version of the hsync input. this signal is always active high. by maintain- ing alignment with datack, datack , and data, data timing with respect to horizontal sync can always be clearly determined. sogout sync on green slicer output the output of the sync on green slicer comparator. when sogin is presented with a dc-coupled ground-referenced analog graphics signal containing composite sync, sogout will produce a digital composite sync signal. this signal gets no other processing on the ad9884a. the sog slicer comparator continues to operate when the ad9884a is put into a power-down state. control sda serial data i/o bidirectional data port for the serial interface port. scl serial interface clock clock input for the serial interface port. a 1C0 serial port address lsbs the two least significant bits of the serial port address are set by the logic levels on these pins. connect a pin to ground to set the address bit to 0. tie it high (to v d through 10 k w ) to set the address bit to 1. using these pins, the serial address may be set to any value from 98h to 9fh. up to four ad9884as may be used on the same serial bus by appropriately setting these bits. they can also be used to change the ad9884a address if a conflict is found with another device on the bus. pwrdn power-down control input bringing this pin low puts the ad9884a into a very low power dissipation mode. the output buffers are placed in a high impedance state. the clock generator is stopped. the control register contents are maintained. the sync on green slicer (sogout) and internal reference continue to function.
rev. b ad9884a C8C pin function descriptions (continued) pin name function analog interface refout internal reference output output from the internal 1.25 v bandgap reference. this output is intended to drive relatively light loads. it can drive the ad9884a reference input directly, but should be externally buffered if it is used to drive other loads as well. the absolute accuracy of this output is 4%, and the temperature coefficient is 50 ppm, which is adequate for most ad9884a applications. if higher accuracy is required, an external reference may be employed. if an exter- nal reference is used, tie this pin to ground through a 0.1 m f capacitor. refin reference input the reference input accepts the master reference voltage for all ad9884a internal circuitry (+1.25 v 10%). it may be driven directly by the refout pin. its high impedance presents a very light load to the reference source. this pin should be bypassed to ground with a 0.1 m f capacitor. filt external filter connection for proper operation, the pixel clock generator pll requires an external filter. connect the filter shown in figure 10 to this pin. for optimal performance, minimize noise and parasitics on this node. power supply v d main power supply these pins supply power to the main elements of the circuit. it should be as quiet and filtered as possible. v dd digital output power supply a large number of output pins (up to 52) switching at high speed (up to 140 mhz) generates a lot of power supply transients (noise). these supply pins are identified separately from the v d pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. if the ad9884a is interfacing with lower- voltage logic, v dd may be connected to a lower supply voltage (as low as 2.5 v) for compatibility. pv d clock generator power supply the most sensitive portion of the ad9884a is the clock generation circuitry. these pins provide power to the clock pll and help the user design for optimal performance. the designer should provide quiet, noise-free power to these pins. gnd ground the ground return for all circuitry on chip. it is recommended that the ad9884a be assembled on a single solid ground plane, with careful attention to ground current paths. see the design guide for details.
rev. b ad9884a C9C control register map the ad9884a is initialized and controlled by a set of registers that determine the operating modes. an external controller is employed to write and read the control registers through the 2-line serial interface port. table ii. control register map reg bit default mnemonic function pll divider control 00 7C0 01101001 plldivm pll divide ratio msbs 01 7C4 1101 ???? plldivl pll divide ratio lsbs 01 3C0 ???? 0000 reserved, set to zero input gain 02 7C0 10000000 redgain red channel gain adjust 03 7C0 10000000 grngain green channel gain ad just 04 7C0 10000000 blugain blue channel gain adjust input offset 05 7C2 100000 ?? redofst red channel offset adjust 05 1C0 ?????? 00 reserved, set to zero 06 7C2 100000 ?? grnofst green channel offset adjust 06 1C0 ?????? 00 reserved, set to zero 07 7C2 100000 ?? bluofst blue channel offset adjust 07 1C0 ?????? 00 reserved, set to zero clamp timing 08 7C0 10000000 clplace clamp placement 09 7C0 10000000 cldur clamp duration general control 1 0a 7 1 ??????? demux output port select 0a 6 ? 1 ?????? par output timing select 0a 5 ?? 1 ????? hspol hsync polarity 0a 4 ??? 1 ???? cstpol coast polarity 0a 3 ???? 0 ??? extclmp clamp signal source 0a 2 ????? 1 ?? clampol clamp signal polarity 0a 1 ?????? 0 ? extclk external clock select 0a 0 ??????? 0 reserved, set to zero clock generator control 0b 7C3 10000 ??? phase clock phase adjust 0b 2C0 ????? 000 reserved, set to zero 0c 7 0 ??????? reserved, set to zero 0c 6C5 ? 01 ????? vcornge vco range select 0c 4C2 ??? 001 ?? current charge pump current 0c 1C0 ?????? 00 reserved, set to zero general control 2 0d 7C5 000 ????? reserved, set to zero 0d 4 ??? 0 ???? outphase o utput port phase 0d 3C1 ???? 000 ? revid die revision id 0d 0 ??????? 0 reserved, set to zero 0e 7C0 00000000 reserved, set to zero table iii. default register values reg value reg value 00 01101001 69h 08 10000000 80h 01 1101 0000 d0h 09 10000000 80h 02 10000000 80h 0a 11110100 f4h 03 10000000 80h 0b 10000 000 80h 04 10000000 80h 0c 0 01 001 00 24h 05 100000 00 80h 0d 00000000 00h 06 100000 00 80h 0e 0000xxx0 0xh 07 100000 00 80h 0f 00000000 00h control register detail pll divider control 00 7C0 plldivm pll divide ratio msbs the eight most significant bits of the 12-bit pll divide ratio plldiv. the operational divide ratio is plldiv + 1. the pll derives a master clock from an incoming hsync signal. the master clock frequency is then divided by an integer value, and the dividers output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. this is typically 20% to 30% more than the number of active pixels in the display. the 12-bit value of plldiv supports divide ratios from 2 to 4095. the higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed hsync frequency. vesa has established some standard timing specifications, which will assist in determining the value for plldiv as a function of horizontal and vertical display resolution and frame rate (table vii). however, many computer systems do not conform precisely to the recommendations, and these numbers should be used only as a guide. the display system manufac- turer should provide automatic or manual means for optimizing plldiv. an incorrectly set plldiv will usually produce one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. the power-up default value of plldiv is 1693 (plldivm = 69h, plldivl = dxh). 01 7C4 plldivl pll divide ratio lsbs the four least significant bits of the 12-bit pll divide ratio plldiv . the operational divide ratio is plldiv + 1. the power-up default value of plldiv is 1693 (plldivm = 69h, plldivl = dxh).
rev. b ad9884a C10C input gain 02 7C0 redgain red channel gain adjust an 8-bit word that sets the gain of the red channel. the ad9884a can accommodate input signals with a full-scale range of between 0.5 v and 1.0 v p-p. setting redgain to 255 corresponds to an input range of 1.0 v. a redgain of 0 establishes an input range of 0.5 v. note that increasing redgain results in the picture having less contrast (the input signal uses fewer of the available converter codes). see figure 8. the power-up default value is redgain = 80h. 03 7C0 grngain green channel gain adjust an 8-bit word that sets the gain of the green channel. see redgain (02). the power-up default value is grngain = 80h. 04 7C0 blugain blue channel gain adjust an 8-bit word that sets the gain of the blue channel. see redgain (02). the power-up default value is blugain = 80h. input offset 05 7C2 redofst red channel offset adjust a six-bit offset binary word that sets the dc offset of the red channel. one lsb of offset adjustment equals approximately one lsb change in the adc offset. therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel is changed (figure 9). a nominal setting of 31 results in the channel nomi- nally clamping the back porch (during the clamping interval) to code 00. an offset setting of 63 results in the channel clamping to code 31 of the adc. an offset setting of 0 clamps to code C31 (off the bottom of the range). increasing the value of redofst decreases the brightness of the channel. the power-up default value is redofst = 80h. 06 7C2 grnofst green channel offset adjust a six-bit offset binary word that sets the dc offset of the green channel. see redofst (05). the power-up default value is grnofst = 80h. 07 7C2 bluofst blue channel offset adjust a six-bit offset binary word that sets the dc offset of the green channel. see redofst (05). the power-up default value is bluofst = 80h. clamp timing 08 7C0 clplace clamp placement an 8-bit register that sets the position of the internally generated clamp. when extclmp = 0, a clamp signal is generated internally, at a position established by clplace and for a duration set by cldur. clamping is started clplace pixel periods after the trailing edge of hsync. clplace may be programmed to any value between 1 and 255. clplace = 0 is not supported. the clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between hsync and the image. a value of 08h will usually work. when extclmp = 1, this register is ignored. the power-up default value is clplace = 80h. 09 7C0 cldur clamp duration an 8-bit register that sets the duration of the internally gener- ated clamp. when extclmp = 0, a clamp signal is generated internally, at a position established by clplace and for a duration set by cldur. clamping is started clplace pixel periods after the trailing edge of hsync, and continues for cldur pixel peri- ods. cldur may be programmed to any value between 1 and 255. cldur = 0 is not supported. for the best results, the clamp duration should be set to include the majority of the black reference signal time found following the hsync signal trailing edge. insufficient clamping time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the average picture level (apl), or brightness. a value of 10h to 20h works with most standard signals. when extclmp = 1, this register is ignored. the power-up default value is cldur = 80h.
rev. b ad9884a C11C general control 0a 7 demux output port select a bit that determines whether all pixels are presented to a single port (a), or alternating pixels are demultiplexed to ports a and b. demux function 0 all data goes to port a 1 alternate pixels go to port a and port b when demux = 0, port b outputs are in a high impedance state. the power-up default value is demux = 1. 0a 6 parallel output timing select setting this bit to a logic 1 delays data on port a and the datack output by one-half datack period so that the rising edge of datack may be used to externally latch data from both port a and port b. when this bit is set to a logic 0, the rising edge of datack may be used to externally latch data from port a only, and the datack rising edge may be used to externally latch data from port b. parallel function 0 data alternates between ports 1 simultaneous data on alternate datacks when in single port mode (demux = 0), this bit is ignored. the power-up default value is parallel = 1. 0a 5 hspol hsync polarity a bit that must be set to indicate the polarity of the hsync signal that is applied to the hsync input. hspol function 0 active low 1 active high active low is the traditional negative-going hsync pulse. sampling timing is based on the leading edge of hsync, which is the falling edge. the clamp position, as determined by clplace, is measured from the trailing edge. active high is inverted from the traditional hsync, with a positive-going pulse. this means that sampling timing will be based on the leading edge of hsync, which is now the ris- ing edge, and clamp placement will count from the falling edge. the device will operate more-or-less properly if this bit is set incorrectly, but the internally generated clamp position, as es- tablished by clpos, will not be placed as expected, which may generate clamping errors. the power-up default value is hspol = 1. 0a 4 cstpol coast polarity a bit that must be set to indicate the polarity of the coast signal that is applied to the coast input. cstpol function 0 active low 1 active high active low means that the clock generator will ignore hsync inputs when coast is low, and continue operating at the same nominal frequency until coast goes high. active high means that the clock generator will ignore hsync inputs when coast is high, and continue operating at the same nominal frequency until coast goes low. the power-up default value is cstpol = 1. 0a 3 extclmp clamp signal source a bit that determines the source of clamp timing. extclmp function 0 internally-generated clamp 1 externally-provided clamp signal a 0 enables the clamp timing circuitry controlled by clplace and cldur. the clamp position and duration is counted from the trailing edge of hsync. a 1 enables the external clamp input pin. the three channels are clamped when the clamp signal is active. the polarity of clamp is determined by the clampol bit. the power-up default value is extclmp = 0. 0a 2 clampol clamp signal polarity a bit that determines the polarity of the externally provided clamp signal. clampol function 0 active low 1 active high a 0 means that the circuit will clamp when clamp is low, and it will pass the signal to the adc when clamp is high. a 1 means that the circuit will clamp when clamp is high, and it will pass the signal to the adc when clamp is low. the power-up default value is clampol = 1. 0a 1 extclk external clock select a bit that determines the source of the pixel clock. extclk function 0 internally generated clock 1 externally provided clock signal a 0 enables the internal pll that generates the pixel clock from an externally-provided hsync. a 1 enables the external ckext input pin. in this mode, the pll divide ratio (plldiv) is ignored. the clock phase adjust (phase) is still functional. the power-up default value is extclk = 0.
rev. b ad9884a C12C clock generator control 0b 7C3 phase clock phase adjust a five-bit value that adjusts the sampling phase in 32 steps across one pixel time. each step represents an 11.25 degree shift in sampling phase. the power-up default value is phase = 16. 0c 6C5 vcornge vco range select two bits that establish the oper ating range of the clock generator. vcornge range (mhz) 00 20-60 01 50-90 10 80-120 11 110-140 vcornge must be set to correspond with the desired operat- ing frequency (incoming pixel rate). the power-up default value is vcornge = 01. 0c 4C2 current charge pump current three bits that establish the current driving the loop filter in the clock generator. current current ( m a) 000 50 001 100 010 150 011 250 100 350 101 500 110 750 111 1500 current must be set to correspond with the desired operat- ing frequency (incoming pixel rate). the power-up default value is current = 001. 0d 4 outphase output port phase one bit that determines whether even pixels or odd pixels go to port a. outphase first pixel after hsync 0 port a 1 port b in normal operation (outphase = 0), when operating in dual channel output mode (demux = 1), the first sample after the hs ync leading edge is presented at port a. every subsequent odd sample appears at port a. all even samples go to port b. when outphase = 1, these ports are reversed and the first sample goes to port b. when demux = 0, this bit is ignored. when reading back the value of outphase, the bit appears at register 0d, bit 7. 0d 3C1 revid silicon revision id the die revision of the ad9884a can be determined by reading these three bits. serial control port a 2-wire serial control interface is provided. up to four ad9884a devices may be connected to the 2-wire serial interface, with each device having a unique address. the 2-wire interface comprises a clock (scl) and a bidirec- tional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. there are six components to serial bus operation: ? start signal ? slave address byte ? base register address byte ? data byte to read or write ? stop signal when the serial interface is inactive (scl and sda are high) communications are initiated by sending a start signal. the start signal is a high-to-low transition on sda while scl is high. this signal alerts all slaved devices that a data transfer sequence is coming. the first eight bits of data transferred after a start signal com- prising a seven bit slave address (the first seven bits) and a single r/ w bit (the eighth bit). the r/ w bit indicates the direc- tion of data transfer, read from (1) or write to (0) the slave device. if the transmitted slave address matches the address of the device (set by the state of the sa 1-0 input pins in table iv ), the ad9884a acknowledges by bringing sda low on the ninth scl pulse. if the addresses do not match, the ad9884a does not acknowledge. table iv. serial port addresses bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 r/ w (msb) (lsb) 1 001100 1 001101 1 001110 1 001111 data transfer via serial interface for each byte of data read or written, the msb is the first bit of the sequence. if the ad9884a does not acknowledge the master device during a write sequence, the sda remains high so the master can generate a stop signal. if the master device does not acknowl- edge the ad9884a during a read sequence, the ad9884a inter- prets this as end of data. the sda remains high so the master can generate a stop signal.
rev. b ad9884a C13C writing data to specific control registers of the ad9884a requires that the 8-bit address of the control register of interest be written after the slave address has been established. this control register address is the base address for subsequent write operations. the base address autoincrements by one for each byte of data written after the data byte intended for the base address. if more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 0eh. any base address higher than 0eh will not produce an acknowledge signal. data are read from the control registers of the ad9884a in a similar manner. reading requires two data transfer operations: the base address must be written with the r/ w bit of the slave address byte low to set up a sequential read operation. reading (the r/ w bit of the slave address byte high) begins at the previously established base address. the address of the read register autoincrements after each byte is transferred. to terminate a read/write sequence to the ad9884a, a stop signal must be sent. a stop signal comprises a low-to-high transition of sda while scl is high. a repeated start signal occurs when the master device driving the serial interface generates a start signal without first generat- ing a stop signal to terminate the current communication. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. serial interface read/write examples write to one control register ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? stop signal t stosu t dah sda scl t buff t stah t dho t dsu t dal t stasu figure 1. serial port read/write timing sda scl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ack figure 2. serial interfacetypical byte transfer write to four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? data byte to (base address + 1) ? data byte to (base address + 2) ? data byte to (base address + 3) ? stop signal read from one control register ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? stop signal read from four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? data byte from (base address + 1) ? data byte from (base address + 2) ? data byte from (base address + 3) ? stop signal
rev. b ad9884a C14C frequency C mpps 400 0 100 20 mw 40 60 80 700 600 500 800 120 140 160 figure 3. power dissipation vs. frequency design guide general description the ad9884a is a fully-integrated solution for capturing analog rgb signals and digitizing them for display on flat panel moni- tors or projectors. the circuit is also ideal for providing a com- puter interface for hdtv monitors or as the front-end to high performance video scan converters. implemented in a high performance cmos process, the inter- face can capture signals with pixel rates of up to 140 megapixels per second (mpps), and with an alternate pixel sampling mode, up to 280 mpps. v d r in b in g in 355 v figure 4. equivalent analog input circuit v d digital input 360 v figure 5. equivalent digital input circuit v d digital output figure 6. equivalent digital output circuit the ad9884a includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. all controls are programmable via a 2-wire serial interface. full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. with a typical power dissipation of only 570 mw and an operat- ing temperature range of 0 c to 70 c, the device requires no special environmental considerations. input signal handling analog inputs the ad9884a has three high impedance analog input pins for the red, green, and blue channels. they will accommodate signals ranging from 0.5 v to 1.0 v p-p. signals are typically brought onto the interface board via a 15- pin d connector, a vesa p&d connector, a ddwg dvi connector, or via bnc connectors. the ad9884a should be located as close as practical to the input connector. signals should be routed via matched- impedance traces (normally 75 w ) to the ic input pins. at that point the signal should be resistively terminated (75 w to the signal ground return) and capacitively coupled to the ad9884a inputs through 47 nf capacitors. these capacitors form part of the dc restoration circuit. in an ideal world of perfectly matched impedances, the best performance can be obtained with the widest possible signal bandwidth. the ultrawide bandwidth inputs of the ad9884a (500 mhz) can track the input signal continuously as it moves from one pixel level to the next, and digitize the pixel during a long, flat pixel time. in many systems, however, there are mis- matches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. this makes it more difficult to establish a sampling phase that provides good image quality. it has been shown that a small inductor in series with the input is effective in rolling off the input bandwidth slightly, and providing a high quality signal over a wider range of conditions. using a fair-rite #2508051217z0 high-speed signal chip bead inductor in the circuit of figure 7 gives good results in most applications. r ain g ain b ain rgb input 47nf 75 v figure 7. analog input interface circuit hsync, vsync inputs the interface also takes a horizontal sync signal, which is used to generate the pixel clock and clamp timing. it is possible to operate the ad9884a without applying hsync (using an external clock, external clamp, and single port output mode) but a number of features of the chip will be unavailable, so it is recommended that hsync be provided. this can be either a sync signal directly from the graphics source, or a preprocessed ttl or cmos level signal. the hsync input includes a schmitt trigger buffer for immunity to noise and signals with long rise times.
rev. b ad9884a C15C in typical pc-based graphic systems, the sync signals are simply ttl-level drivers feeding unshielded wires in the monitor cable. since the ad9884a operates from a 3.3 v power supply, and ttl sources may drive a high level to 5 v or more, it is recommended that a 1 k w series current-limiting resistor be placed in series with hsync and coast. if these pins are driven more than 0.5 v outside the power supply voltages, internal esd protection diodes will conduct, and may dissipate consid- erable power if the sync source is of particularly low impedance. if a signal is applied to the ad9884a when the ics power is off, then even a 1 v signal can turn on the esd protection diodes. the 1 k w series resistor will protect the device from overstress in this situation as well. serial control port the serial control port (sda, scl) is designed for 3.3 v logic. if there are 5 v drivers on the bus, these pins should be pro- tected with 150 w series resistors. output signal handling the digital outputs are designed and specified to operate from a 3.3 v power supply (v dd ). they can also work with a v dd as low as 2.5 v for compatibility with other 2.5 v logic. clamping to properly digitize the incoming signal, the dc offset of the input signal must be adjusted to fit the range of the on-board a/d converters. most graphic systems produce rgb signals with black at ground and white at approximately +0.75 v. however, if sync signals are embedded in the graphics, then the sync tip is often at ground potential, and black is at +300 mv. then white is at approxi- mately +1.0 v. some common rgb line amplifier boxes use emitter-follower buffers to split signals and increase drive capa- bility. this introduces a 700 mv dc offset to the signal which must be removed for proper capture by the ad9884a. the key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. an offset is then introduced which results in the a/d converters producing a black output (code 00h) when the known black input is present. that offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. in most graphic systems, black is transmitted between active video lines. going back to crt displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace) and a black signal is pro- vided to prevent the beam from disturbing the image. in systems with embedded sync, a blacker-than-black signal (hsync) is produced briefly to signal the crt that it is time to begin a retrace. for obvious reasons, it is important to avoid clamping on the tip of hsync. fortunately, there is virtually always a period following hsync called the back porch where a good black reference is provided. t his is the time when clamp- ing should be done. the clamp timing can be established by simply exercising the clamp pin at the appropriate time (with extclmp = 1). the polarity of this signal is set by the clampol bit. a simpler method of clamp timing employs the ad9884a inter- nal clamp timing generator. register clplace is programmed with the number of pixel times that should pass after the trailing edge of hsync before clamping starts. a second register (cldur) sets the duration of the clamp. these are both 8-bit values, providing considerable flexibility in clamp generation. the clamp timing is referenced to the trailing edge of hsync because, though hsync duration can vary widely, the back porch (black reference) always follows hsync. a good start- ing point for establishing clamping is to set clplace to 08h (providing 8 pixel periods for the graphics signal to stabilize after sync) and set cldur to 14h (giving the clamp 20 pixel periods to reestablish the black reference). clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. the value of this capaci- tor affects the performance of the clamp. if it is too small, there will be a significant amplitude change during a horizontal line time (between clamping intervals). if the capacitor is too large, then it will take excessively long for the clamp circuit to recover from a large change in incoming signal offset. the recommended value results in recovering from a step error of 100 mv to within 1/2 lsb in 10 lines with a clamp duration of 20 pixels on a 60 hz sxga signal. gain and offset control the ad9884a can accommodate input signals with inputs ranging from 0.5 v to 1.0 v full scale. the full-scale range is set in three 8-bit registers (redgain, grngain, blugain). a code of 0 in a gain register establishes a minimum input range of 0.5 v; 255 corresponds with the maximum range of 1.0 v. note that increasing the gain setting results in an image with less contrast. the offset control shifts the entire input range, resulting in a change in image brightness. three 6-bit registers (redofst, grnofst, bluofst) provide independent settings for each channel. the offset controls provide a 31 lsb adjustment range. this range is connected with the full-scale range, so if the input range is doubled (from 0.5 v to 1.0 v) then the offset step size is also doubled (from 2 mv per step to 4 mv per step). figure 8 illustrates the interaction of gain and offset controls. the magnitude of an lsb in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. the change is minimal if the offset setting is near midscale. when changing the offset, the full-scale range is not affected, but the full -scale level is shifted by the same amount as the zero scale level.
rev. b ad9884a C16C input range 1.0v 0.0v 0.5v offset = 1fh offset = 3fh offset = 0fh offset = 1fh offset = 3fh offset = 0fh gain 00h ffh figure 8. gain and offset control clock generation a phase locked loop (pll) is employed to generate the pixel clock. in this pll, the hsync input provides a reference frequency. a voltage controlled oscillator (vco) generates a much higher pixel clock frequency. this pixel clock is divided by the value plldiv programmed into the ad9884a, and phase compared with the hsync input. any error is used to shift the vco frequency and maintain lock between the two signals. the stability of this clock is a very important element in provid- ing the clearest and most stable image. during each pixel time, there is a period during which the signal is slewing from the old pixel amplitude and settling at its new value. then there is a time when the input voltage is stable, before the signal must slew to a new value (figure 9). the ratio of the slewing time to the stable time is a function of the bandwidth of the graphics dac and the bandwidth of the transmission system (cable and termination). it is also a function of the overall pixel rate. clearly, if the dynamic characteristics of the system remain fixed, then the slewing and settling time is likewise fixed. this time must be subtracted from the total pixel period, leaving the stable period. at higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well. any jitter in the pixel clock reduces the precision with which the sampling time can be determined, and must also be subtracted from the stable pixel time. pixel clock invalid sample times figure 9. pixel sampling times considerable care has been taken in the design of the ad9884as clock generation circuit to minimize jitter. as indicated in fig- ure 11 and table vi, the clock jitter of the ad9884a is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. the pll characteristics are determined by the loop filter de- sign, by the pll charge pump current (current), and by the vco range setting (vcornge). the loop filter design is illustrated in figure 10. recommended settings of vcornge and current for vesa standard display modes are listed in table vii. table v. typical k vco derived from vcornge pixel rate (mhz) vcornge k vco (mhz/v) 20C60 00 100 50C90 01 100 80C120 10 150 110C140 11 180 0.039 m f 3.3k v c p 0.0039 m f pv d filt c z r z figure 10. pll loop filter detail table vi. pixel clock jitter vs frequency pixel rate jitter p-p jitter p-p (msps) (ps) (% of pixel time) 135 350 4.7% 108 400 4.3% 94 400 3.4% 75 450 3.4% 65 600 3.9% 50 500* 2.4% 40 500* 2.0% 36 550* 1.8% 25 1000* 2.5% *ad9884a in oversampled mode.
rev. b ad9884a C17C table vii. recommended vcornge and current settings for standard display formats refresh horizontal standard resolution rate frequency pixel rate vcornge current vga 640 480 60 hz 31.5 khz 25.175 mhz 00 000 72 hz 37.7 khz 31.500 mhz 00 000 75 hz 37.5 khz 31.500 mhz 00 000 85 hz 43.3 khz 36.000 mhz 00 001 svga 800 600 56 hz 35.1 khz 36.000 mhz 00 001 60 hz 37.9 khz 40.000 mhz 00 001 72 hz 48.1 khz 50.000 mhz 00 010 75 hz 46.9 khz 49.500 mhz 00 001 85 hz 53.7 khz 56.250 mhz 01 010 xga 1024 768 60 hz 48.4 khz 65.000 mhz 01 010 70 hz 56.5 khz 75.000 mhz 01 011 75 hz 60.0 khz 78.750 mhz 01 011 80 hz 64.0 khz 85.500 mhz 10 011 85 hz 68.3 khz 94.500 mhz 10 011 sxga 1280 1024 60 hz 64.0 khz 108.000 mhz 10 011 75 hz 80.0 khz 135.000 mhz 11 100 85 hz 91.1 khz 157.500 mhz* 01 100 uxga 1600 1200 60 hz 75.0 khz 162.000 mhz* 01 100 65 hz 81.3 khz 175.500 mhz* 10 100 70 hz 87.5 khz 189.000 mhz* 10 101 75 hz 93.8 khz 202.500 mhz* 10 101 85 hz 106.3 khz 229.500 mhz* 10 110 vesa monitor timing standards and guidelines, september 17, 1998 *graphics sampled at 1/2 incoming pixel rate using alternate pixel sampling mode. figure 11 illustrates the ad9884as jitter as a percentage of the total clock period over the range of operating frequencies. though the jitter is very low over most of the range (less than 5% of the pixel period), the jitter increases at clock rates below 40 mhz. at lower frequencies, the jitter can be reduced by operating the ad9884a at twice the desired frequency, and using only every other data sample produced. this can be easily implemented by placing the part in dual channel mode (for example, as in figure 21), and reading the data from only one of the output ports. the datack and datack outputs will run at the desired, lower, sample rate. pixel clock C mhz 0 0 100 20 jitter C % 40 60 80 120 140 160 5 15 10 jitter p-p (%) oversampled rate jitter p-p (%) figure 11. pixel clock jitter vs. frequency
rev. b ad9884a C18C two things happen to horizontal sync in the ad9884a. first, hsout is always produced in an active high state: that is, the leading edge of hsout is always a rising edge. then, hsout is aligned with datack and the data outputs. this is the sync signal that should be used to drive the rest of the dis- play system. the trailing edge of hsout is not time-aligned: it remains linked to the incoming hsync. refer to the timing diagrams for hsout leading edge placement. hsout trailing edge is coincident with hsync input trailing edge. there can be no guarantee of the timing relationship between the hsout trail- ing edge and datack. therefore, the leading edge of hsout should be used for all display system timing. hsout is forced low at midline, whether or not the incom- ing hsync trailing edge has arrived. if hsout exhibits a 50% duty cycle (while hsync input does not) it is an indica- tion that the hspol bit is incorrectly set. this characteristic can be used to produce an hsout with synchronous leading and trailing edges by programming hspol to use the trailing edge of hsync instead of the leading edge. in this case, if the internal clamp function is used, be aware that the clamp posi- tion is now measured from the leading edge of hsync, and program it accordingly. coast timing in most computer systems, the hsync signal is provided con- tinuously on a dedicated wire. in these systems, the coast input and function are unnecessary, and should not be used. in some systems, however, hsync is disturbed during the vertical sync period (vsync). in some cases, hsync pulses disappear. in other systems, such as those that employ compos- ite sync (csync) signals or embed sync on green (sog), hsync includes equalization pulses or other distortions during vsync. to avoid upsetting the clock genera tor during vsync, it is important to ignore these distortions. if the pixel clock pll sees extraneous pulses, it will attempt to lock to this new fre- quency, and will have changed frequency by the end of the vsync period. it then will take a few lines of correct hsync timing to recover at the beginning of a new frame, resulting in a tearing of the image at the top of the display. the coast input is provided to eliminate this problem. it is an asynchronous input that disables the pll input and allows the clock to free-run at its then-current frequency. the pll can free-run for several lines without significant frequency drift. coast can be driven directly from a vsync input, or it can be provided by the graphics controller. timing the following timing diagrams show the operation of the ad9884a in all clock modes. the part establishes timing by having the sample that corresponds to the pixel digitized when the leading edge of hsync occurs sent to the a data port (to the b data port if 0dh, bit 4 = 1). in dual channel mode, the next sample is sent to the b port (to the a data port if 0dh, bit 4 = 1). subsequent samples are alternated between the a and b data ports. in single channel mode, data is only sent to the a data port, and the b port is placed in a high im- pedance state. when operating in dual channel mode, since the first pixel after hsync is always sent to the a port, there are situations where the first desired pixel (the first active pixel of a line) may appear on the b port. if the graphics controller or memory buffer requires that the first pixel appear on the a port, the outphase control bit will swap the data to the a and b ports. the output data clock signal is created so that its rising edge always occurs between a data transitions, and can be used to latch the output data externally. the hsync output is pipelined with the data in a fixed timing relationship between the two in all single channel modes. there is a pipeline in the ad9884a, which must be flushed before valid data becomes available. in all single channel modes, four data sets are presented before valid data is avail- able. in all dual channel modes, two data sets are presented before valid a port data is available. t per t dcycle t skew datack datack data hsout figure 12. output timing horizontal sync timing horizontal sync is processed in the ad9884a to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. the hsync input is used as a reference to generate the pixel sampling clock. the sampling phase can be adjusted, with re- spect to hsync, through a full 360 in 32 steps via the phase register (to optimize the pixel sampling time). display systems use hsync to align memory and display write cycles, so it is important to have a stable timing relationship between hsout and datack.
rev. b ad9884a C19C o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 figure 14. odd pixels from frame 1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 figure 15. even pixels from frame 2 alternate pixel sampling mode a logic 1 input on ckinv (pin 27) shifts the sampling phase 180 degrees. ckinv can be switched between frames to imple- ment the alternate pixel sampling mode. this allows higher effective image resolution to be achieved at lower pixel rates, but with lower frame rates. o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e o o o o o o o o o o o e e e e e e e e e e e figure 13. odd and even pixels in a frame on one frame, only even pixels are digitized. on the subsequent frame, odd pixels are sampled. by reconstructing the entire frame in the graphics controller, a complete image can be reconstructed. this is very similar to the interlacing process that is employed in broadcast television systems, but the interlacing is vertical instead of horizontal. the frame data is still presented to the display at the full desired refresh rate (usually 60 hz) so there are no flicker artifacts added. o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 figure 16. combined frame output from graphics controller o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 figure 17. subsequent frame from controller
rev. b ad9884a C20C rgbin hsync pxck hs adcck datack douta hsout p6 p0 p1 p2 p3 p4 p5 d6 d0 d1 d2 d3 d4 d5 p7 d7 5 pipe delay figure 18. single channel mode rgbin hsync pxck hs adcck datack douta hsout p6 p0 p1 p2 p3 p4 p5 d2 d4 d6 5 pipe delay d0 p7 figure 19. single channel mode, alternate pixel sampling (even pixels) p6 rgbin p0 p1 p2 p3 p4 p5 d7 d1 d3 d5 hsync pxck hs adcck datack douta hsout 5.5 pipe delay p7 figure 20. single channel mode, alternate pixel sampling (odd pixels) p6 rgbin p0 p1 p2 p3 p4 p5 d6 d0 d1 d2 d3 d4 d5 hsync pxck hs adcck datack douta hsout p7 d7 doutb 5 pipe delay figure 21. dual channel mode, interleaved outputs
rev. b ad9884a C21C p6 rgbin p0 p1 p2 p3 p4 p5 d1 d3 d5 hsync pxck hs adcck datack douta hsout p7 d7 d0 d2 d4 d6 6 pipe delay figure 22. dual channel mode, parallel outputs p6 rgbin p0 p1 p2 p3 p4 p5 d0 d2 d4 d6 hsync pxck hs adcck datack douta hsout doutb 5 pipe delay p7 figure 23. dual channel mode, interleaved outputs, alternate pixel sampling (even pixels) p6 rgbin p0 p1 p2 p3 p4 p5 hsync pxck hs adcck datack douta hsout doutb d3 d1 d7 d5 p7 5.5 pipe delay figure 24. dual channel mode, interleaved outputs, alternate pixel sampling (odd pixels) p6 rgbin p0 p1 p2 p3 p4 p5 hsync pxck hs adcck datack douta hsout doutb d0 d4 d2 d6 6 pipe delay p7 figure 25. dual channel mode, parallel outputs, alternate pixel sampling (even pixels)
rev. b ad9884a C22C pcb layout recommendations the ad9884a is a high precision, high speed analog device. as such, to get the maximum performance out of the part it is important to have a well laid-out board. inputs using the following layout techniques on the graphics inputs is extremely important: minimize the trace length running into the graphics inputs. this is accomplished by placing the ad9884a as close as possible to the input connector. long input trace lengths are undesirable because they will pick up more noise from the board and other external sources. place the 75 w termination resistors as close to the ad9884a as possible. any additional trace length between the termination resistors and the input of the ad9884a increases the magnitude of reflections, which will corrupt the graphics signal. use 75 w matched impedance traces. trace impedances other than 75 w will also increase the magnitude of reflections. the ad9884a has very high input bandwidth (500 mhz). while this is desirable for acquiring a high resolution pc graphics signal with fast edges, it means that it will also capture any high frequency noise present. therefore, it is important to reduce the amount of noise that gets coupled to the inputs. avoid running any digital traces near the analog inputs. due to the high bandwidth of the ad9884a, sometimes low- pass filtering the analog inputs can help to reduce noise. (for many applications, filtering is unnecessary.) our experiments have shown that placing a series ferrite bead prior to the 75 w termination resistor is helpful in filtering out excess noise. spe- cifically, we used the part #2508051217z0 from fair-rite, but each application may work best with a different bead value. power supply bypassing we recommend you bypass each power supply pin with a 0.1 m f capacitor. the exception is in the case where two or more sup- ply pins are adjacent. for these groupings of powers/grounds, it is only necessary to have one bypass capacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the ad9884a, as that interposes resistive vias in the path. the bypass capacitors should be connected between the power plane and the power pin. current should flow from the power plane ? capacitor ? power pin. do not make the power connec- tion between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful attention to regulation, filtering, and bypassing. it is highly desirable to provide a separately regulated supply for the analog circuitry (v d and p vd ). some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supp lied to the analog supply regulator, which can in turn produce changes in the regulated analog voltage. this can be mitigated by regulating the analog supply, or at least p vd , from a different, cleaner, power source (for example, from a +12 v supply). we also recommend that you use a single ground plane for the entire board. experience has repeatedly shown that the noise performance is better, or at least the same, with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. p6 rgbin p0 p1 p2 p3 p4 p5 hsync pxck hs adcck datack douta hsout doutb d3 d7 d1 d5 6.5 pipe delay p7 figure 26. dual channel mode, parallel outputs, alternate pixel sampling (odd pixels)
rev. b ad9884a C23C in some cases, using separate ground planes is unavoidable. for those cases, we recommend to at least place a single ground plane under the ad9884a. the location of the split should be at the receiver of the digital outputs. for this case it is even more important to place components wisely because the current loops will be much longer, (current takes the path of least resis- tance). an example of a current loop: p o w e r p l a n e a d 9 8 8 4 a d i g i t a l o u t p u t t r a c e a n a l o g g r o u n d p l a n e d i g i t a l g r o u n d p l a n e d i g i t a l d a t a r e c e i v e r figure 27. pll place the pll loop filter components as close to the ad9884a pins as possible. do not place any digital or other high frequency traces near these components. use the values suggested in the data sheet with 5% tolerance or less. outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance, which requires more current, which causes more internal digital noise. shorter traces reduce the possibility of reflections. adding a series resistor of value 50 w C200 w can suppress reflections, reduce emi, and reduce the current spikes inside of the ad9884a. if series resistors are used, place them as close to the ad9884a pins as possible, (although try not to add vias or extra length to the output trace in order to get the resistors closer). if possible, limit the capacitance that each of the digital outputs drives to less than 10 pf. this can easily be accomplished by keeping traces short and by connecting the outputs to only one device. loading the outputs with excessive capacitance will increase the current transients inside of the ad9884a, and create more digital noise on its power supplies. digital inputs the digital inputs on the ad9884a were designed to work with 3.3 v signals. connecting 5 v digital signals to the part may cause damage. to accommodate 5 v digital signals, we recom- mend adding a series resistor at the ad9884a pin of 1 k w . the only exception is the two serial interface pins, sda and scl. on these two pins, a resistor value of 150 w should be used and it should be placed between the ad9884a pin and the pull-up resistors. any noise that gets onto the hsync input trace will add jitter to the system, so, try to minimize the trace length and try not to run any digital or other high frequency traces near it. voltage reference bypass with a 0.1 m f capacitor. place it as close to the ad9884a pin as possible. make the ground connection as short as possible. refout is easily connected to refin with a short trace. avoid making this trace any longer than it needs to be. when using an external reference, the refout output, while unused, still needs to be bypassed to ground with a 0.1 m f capacitor to avoid ringing.
rev. b ad9884a C24C c3495aC0C2/00 (rev. b) printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 128-lead plastic quad flatpack (mqfp) (s-128) 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) top view (pins down) 1 38 39 65 64 102 128 103 0.020 (0.50) bsc* 0.685 (17.40) 0.677 (17.20) 0.669 (17.00) 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) 0.921 (23.40) 0.913 (23.20) 0.906 (23.00) seating plane 0.134 (3.40) max 0.041 (1.03) 0.035 (0.88) 0.031 (0.78) 0.003 (0.08) max 0.010 (0.25) min 0.110 (2.80) 0.106 (2.70) 0.102 (2.60) the actual position of each lead is within 0.00315 (0.08) from its ideal position when measured in the lateral direction. center figures are typical unless otherwise noted. the controlling dimensions are in mm. *

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